chip select configuration

[v8dave]

Hi all,

I am having some issues getting memory access to a graphics controller. I have 2 LCD displays with 16 bit bus and 6800 mode interface signals.

I have one working well 100% of the time. It is using the SSD2119 from Solomon Systech and works fine with the following chip select configuration.

Data read access with this display is 250ns min.

Code: Select all

sim.cs[2].cscr = 0xFDB8; 			// 1111 1101 1011 1000

Only 2 addresses are used to select DATA or COMMAND registers.

This is configured for 16 bit access and 15 wait states.

The second LCD uses an SSD1963 controller and just does not seem to work although I have had partial success but only one in every 10 power ups. Not ideal. The bus is the same 16 bit with same 6800 mode control signals. This one is a little faster with data read access of 32ns but the timing diagrams are the same, only this one is faster because of the higher resolution supported.

I have tried the same and less wait states but I get some or no response.

On the logic analyser all timings look correct.

I am wondering if the configuration of the chip selects might be an issue but I have read and tried to understand the MCF5235 manual and all looks correct except I can't seem to figure out the burst mode bits, 4 and 5. I have tried setting them to both 0 and 1 with no difference.

Has anyone got any thoughts on this?

[v8dave]

I seem to have it working now but I can't seem to get reliable reads from the bus. I have configured with 15 wait states as a starter and will trim this down once I get it working.

In the attached images you will see the issue I am getting during read of write. I seem to be getting glitches on the CHIP SELECT and I am wondering if my address setup is the issue here. I chose an address that is not used by anything else, at least it is not supposed to be.

The wider CS2 image is the correct behavour and timing wise it works out correct. The narrow one is less than 5ns and the correct width is 210ns. Well within the timing of the LCD.

This is the chip select init code.

Code: Select all

   

#define LCDBASEADDRESS   ( 0xB0000000 )

void ghw_io_init(void)
{
   /* Insert required target specific code here, if any */


   sim.cs[2].csar = ( LCDBASEADDRESS >> 16 );
   //
   // 15 wait states, AA enabled, 16 bit, BEM enabled,
   //
   sim.cs[2].cscr = 0x3DA0; 			// 15 wait states, no burst
   sim.cs[2].csmr = 0x00000001;		// 0000 0000 0000 0001	64Kbyte address range
}

The data is clocked into and out of the device on the rising edge of CS2

If I disable LCD reading in the driver the LCD works and I get a clean display. The issue is that I need to read the LCD for some functions that handle popup windows etc.

Any ideas would be appreciated...
Dave...

[pbreed]

Which netburner module is this?
(The chipselect stuff varies by device type)

Is there any possibility that you are pulling down on the TA line?

[v8dave]

Hi Paul,

Sorry, I should have stated I was using the MOD5234

I don't have the TA connected externally to the module and I assume it has an internal pullup to prevent erroneous operation?

If I single step the code I get randomly the short bus cycle.

Running at full speed and letting the analyser cycle repeat I can see the random short cycles appearing.

Dave...

[pbreed]

Very strange.
Do you have a scope that could look at this signal rather than a logic analyzer?

How clean and how short is your wiring?

[v8dave]

Hi Paul

Just had a DOH moment.

It was the logic threshold in the analyser settings and setting this to te correct level gives good clean signals. Everything is clean edges and signals.

Still can't get the LCD controller SSD1693 to read back. Writing is fine.

Have emailed the LCD manufacturer for assistance on this.

Cheers
Dave...