chip select configuration
Posted: Fri Sep 30, 2011 7:54 am
Hi all,
I am having some issues getting memory access to a graphics controller. I have 2 LCD displays with 16 bit bus and 6800 mode interface signals.
I have one working well 100% of the time. It is using the SSD2119 from Solomon Systech and works fine with the following chip select configuration.
Data read access with this display is 250ns min.
Only 2 addresses are used to select DATA or COMMAND registers.
This is configured for 16 bit access and 15 wait states.
The second LCD uses an SSD1963 controller and just does not seem to work although I have had partial success but only one in every 10 power ups. Not ideal. The bus is the same 16 bit with same 6800 mode control signals. This one is a little faster with data read access of 32ns but the timing diagrams are the same, only this one is faster because of the higher resolution supported.
I have tried the same and less wait states but I get some or no response.
On the logic analyser all timings look correct.
I am wondering if the configuration of the chip selects might be an issue but I have read and tried to understand the MCF5235 manual and all looks correct except I can't seem to figure out the burst mode bits, 4 and 5. I have tried setting them to both 0 and 1 with no difference.
Has anyone got any thoughts on this?
I am having some issues getting memory access to a graphics controller. I have 2 LCD displays with 16 bit bus and 6800 mode interface signals.
I have one working well 100% of the time. It is using the SSD2119 from Solomon Systech and works fine with the following chip select configuration.
Data read access with this display is 250ns min.
Code: Select all
sim.cs[2].cscr = 0xFDB8; // 1111 1101 1011 1000
This is configured for 16 bit access and 15 wait states.
The second LCD uses an SSD1963 controller and just does not seem to work although I have had partial success but only one in every 10 power ups. Not ideal. The bus is the same 16 bit with same 6800 mode control signals. This one is a little faster with data read access of 32ns but the timing diagrams are the same, only this one is faster because of the higher resolution supported.
I have tried the same and less wait states but I get some or no response.
On the logic analyser all timings look correct.
I am wondering if the configuration of the chip selects might be an issue but I have read and tried to understand the MCF5235 manual and all looks correct except I can't seem to figure out the burst mode bits, 4 and 5. I have tried setting them to both 0 and 1 with no difference.
Has anyone got any thoughts on this?