Instructions out of order?

[pbreed]

Putting your data at 0x02800000 is right up against the SDRAM
I like to leave a gap (I know its not supposed to be necessary, but caching gets kind of weird near the edges.

Try an address 0xC0000000 or so...
Also know that with an 8 bit bus the bits are justified high.
D31-MSB
D24-LSB
D23->D0 unused.


Paul

[pbreed]

Also realize that the data buss is always active, so your comment that the CS happens in the middle of the data bus transactions
is wrong, you do not have exclusive use of the data bus, while your writing to your device the processor can and will be using the
databus to get the next instruction, the data from SDRAM etc....

The data bus is only aimed at your peripheral when your cs is active (low).

Paul

[DBrunermer]

Sorry I didn't get to update this sooner. So I turned off all the optimizations, and while the problem didn't go away, it got much more stable. But as it turns out, the scope may have been a factor. Friday was our annual calibration day, and after the tech tuned up the scope, I started to get different results, much more in line with my expectations. Thank you so much. Dan B.

[tod]

We have two hats in our lab, that sit on pegs until needed. One is emblazoned with "It's the Hardware", the other says "It's the Software". Sounds like we should get one with "It's the Test Equipment"!