I need to reset the GPT counter to 0000 but cannot find the proper control register/bit?
I was thinking about wiring the SYNCx signal to a GPIO pin and manually reseting the timer, but ...
The 2007 version of the 5213 data sheet shows using the SYNCx signal to reset the counter, but the 2010 version does not show the SYNCx signal. Any help would be appreciated.
MOD5213 GPT reset
Re: MOD5213 GPT reset
This is pretty strange, definitely a documentation goof on Freescales part. If you go to the very end of the RM you can see what they changed between rev3 and rev4. All they seem to mention is "Updated GPT block diagram for Internal bus clock."... no mention that they completely removed the SYNCx pins and the or gate connecting them to the reset. There is also no mention of completely removing 18.5.3 which describes the sync pins and their functionality. The GPT count register also seems to have some vague information... "They should be written to only in test (special) mode; writing to them has no effect in
normal modes." with no mention anywhere on test or special mode.
After a little deeper digging I see Chapter 2 of both manuals shows that the sync pins are part of the A2D. The A2D chapter describes how those pins are used to trigger a2d sampling from an external trigger. I now remember using these pins with the A2D previously, not sure if they dual function to work with the GPT but it should be an easy test.
I am a bit surprised to see this counter does not have a normal reset. What are you using the GPT for, maybe there is an easier approach if you need a resettable timer. You can do a software reset of the timer using the channel 3 output compare though this is a bit complex. To do this the TCRE bit should be set in the GPTSCR2 register. Then GPTC3 register should then be set to 0. If channel 3 is already in output compare mode the counter should reset, otherwise you can use the GPCFORC register to force a output compare on channel 3. I haven't tested this but it should work. You may want to try this with the GPT disabled so it doesn't trigger any other events or race cases.
normal modes." with no mention anywhere on test or special mode.
After a little deeper digging I see Chapter 2 of both manuals shows that the sync pins are part of the A2D. The A2D chapter describes how those pins are used to trigger a2d sampling from an external trigger. I now remember using these pins with the A2D previously, not sure if they dual function to work with the GPT but it should be an easy test.
I am a bit surprised to see this counter does not have a normal reset. What are you using the GPT for, maybe there is an easier approach if you need a resettable timer. You can do a software reset of the timer using the channel 3 output compare though this is a bit complex. To do this the TCRE bit should be set in the GPTSCR2 register. Then GPTC3 register should then be set to 0. If channel 3 is already in output compare mode the counter should reset, otherwise you can use the GPCFORC register to force a output compare on channel 3. I haven't tested this but it should work. You may want to try this with the GPT disabled so it doesn't trigger any other events or race cases.