SOMRT DSPI Driver clock phase and polarity using GPIO as CS

[ephogy]

In the DSPI Driver, a call to Init(..) will initialize the SPI almost as expected:

spi()->CR = LPSPI_CR_RST(1); // This statement causes the SPI to reset, Clock polarity and phase are set to 0.

The function returns with clock phase/polarity in 0/0. I then have to trigger the GPIO lines appropriately for the CS of devices on the board. Some of these devices require a clock polarity/phase of 1/1.

The call to Start(..) then appropriately sets the clock polarity/phase, but since the chip selects are already low, this causes a clock transition clocking in an extra bit.

my mitigation, for now, is to modify the DSPI Init function to set the polarity and phase appropriately after the spi()->CR = LPSPI_CR_RST(0);

Would this be considered a bug in the underlying OS?

[TomNB]

Hello ephogy,

With mutiple releases and many products with specific drivers, people will always need to know the nndk version and hardware platform to be able to help. I think that is why this has not had an answer and so many views.