Flexbus configuration

[SeeCwriter]

I am trying to read/write an sram I've connected to the flexbus of a MOD54415, rev 1.9, and it's not working correctly.
The sram is 2M X 16-bits. Module Address lines A1 - A15 are connected to A0 - A14 of the sram, with the balance of the
sram address lines (A16 - A20) connected to I/O pins on the Module. I address the sram as blocks of 64k X 16. The sram BHE
& BHL signaled are connect to BE1 & BE0 on the Module.

The Flexbus configuration registers are set as:

Code: Select all

  sim2.cs[4].cscr = 0x41DA0;					// SRAM1 decoding = 7 wait states, 16 bit bus, data left justified, no burst.
  sim2.cs[4].csar = SRAM1_BASE;				// SRAM1 base address = 0xC0000000
  sim2.cs[4].csmr = 0x003F0001;				// SRAM1 size = 0x3F+1 x 64k = 64x65536 = 4194304 (4Mb), 0001h -> cs "Valid"

When I read the configuration registers just before I do a memory test, the values match what they were originally set to.

My simple memory test is:

Code: Select all

void MemTest()
{
  BYTE pattern[4], result[4];
  DWORD adr;
  
  memset( pattern, 0x55, sizeof(pattern) );
  adr = SRAM1_BASE;  // 0xC0000000
  
  do {
    memset( result, 0, sizeof(result);
    
    // Write to sram
    memcpy( adr, pattern, sizeof(pattern) ); 
    iprintf("W: %x %x %x %x\r\n", pattern[0], pattern[1], pattern[2], pattern[3] );  // printout: 55 55 55 55
    
    // Read from sram
    memcpy( result, adr, sizeof(result) );
    iprintf("R: %x %x %x %x\r\n", result[0],  result[1],  result[2],  result[3] );   // printout: 55 55 0 0

    OSTimeDly(1);

  }
  while( true );
}

I have a small logic analyzer connected. The chip-select, write-enable, and output-enable all look good. For a write, both
BE0 & BE1 both go low, but they are both high for a read. Also there is only one write and one read per loop, where I think there
should be two. It acts like the Flexbus is configured for 32-bit transfers. But I've gone over the CSCR setting and it seems
correct. Did I screw up the configuration somewhere?

I'm using v2.8.1 of the tools.

[dciliske]

What's the SRAM P/N?

(I'm thinking through other fun things as well, just thought I'd start with that, since I'm the oddball who knows things like the Flexbus better than generic things like SRAMs. Guess this is what I get coming from software.)

[SeeCwriter]

sram pn: CY621737EV30LL

Also, I increased the number of bytes to write and read to 8, and I get 2 writes and 2 reads now. So it does appear to be doing 32-bit accesses.

[TomNB]

How did you come up with the base address of 0xC0000000? Did you check the memory map document first?

[SeeCwriter]

Sorry, I screwed up the part number. Try CY62177EV30LL.

I hate track pads!

[SeeCwriter]

According to paragraph 20.3.1 of MCF5441x Reference Manual, Rev 4, there are two addresses ranges available for the Flexbus. 0x0000_0000 - 0x3FFF_FFFF, and 0xC000_0000 - 0xDFFF_FFFF. I chose the upper range.

[dciliske]

Uh... did you actually use the address 0xC000_0000 as your SRAM1_BASE? If so, open the MOD54415 Platform documentation... That's the address for the Flash.

The problem is that if you're actually using 0xC000_0000, CS[0] is going to intercept the transaction. I'm surprised you're not reporting that you also had config record or app image corruption as well...

I moved SRAM1_BASE to 0xC200_0000, and have no issue getting BE0/BE1 to trigger on writes.

-Dan

[pbreed]

For a 16 bit interface.....CANT USE A0

A0 selects which byte......


Paul

[SeeCwriter]

Dan,

Correct. It should have been 0xC2000000. I changed it and now all the control signals look correct. And the first 8-bytes written and read are also correct.

I changed my test routine write 1024 bytes of 0x55, and then read 1024 bytes. This is output from what was read:

Reading:

55 55 55 55 55 55 55 55 31 56 87 52 db 8a 49 0a
55 55 55 55 49 d2 59 d7 0b 3f df 98 86 75 70 cb
55 55 55 55 d1 81 de 10 a8 d6 c0 8f c8 e2 61 9f
55 55 55 55 19 ab 98 c7 a1 5e 3c ff 92 3d 25 08
55 55 55 55 ef 12 6c 81 b1 36 d0 c1 20 ba 36 9e
55 55 55 55 10 02 ad c6 c5 3c a8 51 01 1a d1 8e
55 55 55 55 bf 20 1d 41 da 7a 2c 4c 0b 2a 35 cb
55 55 55 55 08 cc 5c 90 28 54 f4 04 cd 4f b1 66
55 55 55 55 9b 80 00 e8 0e f6 12 0b 68 33 46 56
55 55 55 55 53 eb 4f 33 72 5c 22 08 54 9a 77 d0
55 55 55 55 30 46 02 40 df 46 f4 b4 28 58 66 a2
55 55 55 55 60 bd a8 2b 04 8c 35 81 fc 45 d8 69
55 55 55 55 1a d2 66 90 20 49 c8 d9 04 ac 57 0f
55 55 55 55 e8 d7 20 6b ef 85 e0 cc 1a 9b 76 4a
55 55 55 55 e2 94 70 af 59 09 40 e7 0d 03 57 6e
55 55 55 55 62 56 e6 31 b1 15 95 bd c2 a2 d4 43
55 55 55 55 ff bd 62 32 a9 8a 56 43 28 38 15 81
55 55 55 55 0a 0b 40 12 a9 cc c0 66 aa e6 d4 3a
55 55 55 55 c7 8e 0d 7c 46 2f 29 9a cc 5b e4 6b
55 55 55 55 d9 56 42 02 82 26 29 57 b8 39 0c e6
55 55 55 55 a4 77 01 30 b3 72 a2 95 66 87 65 3b
55 55 55 55 14 86 16 2f a6 40 11 6e 35 0b 0c 63
55 55 55 55 11 ca c2 e8 2f f3 50 da a0 1a 4b 28
55 55 55 55 c9 a2 a9 f3 2f 44 64 9b f5 0f b1 4a
55 55 55 55 01 23 72 12 32 5f 1e b5 0c 81 45 8c
55 55 55 55 2c d2 48 69 33 94 4b af 99 5d b7 d3
55 55 55 55 52 29 72 a2 1b 90 ec 8e 22 7c e0 c0
55 55 55 55 07 4f 2e 5d 06 a8 14 4f 46 58 62 e0
55 55 55 55 6c 95 46 00 b3 e5 d4 88 9a 4c 2b 14
55 55 55 55 c5 43 5e 4e 95 c7 f6 f1 e1 71 a6 8e
55 55 55 55 2f 3f 25 4d ed e9 ac 98 05 5a 56 0d
55 55 55 55 e4 63 36 22 64 8f 47 44 4c bf dc cc
55 55 55 55 1b b0 a0 4c a9 2c 82 56 82 6d d9 01
55 55 55 55 19 66 d7 d7 aa b9 a2 80 54 bd 50 c2
55 55 55 55 00 71 29 02 14 42 56 53 c6 2b a2 03
55 55 55 55 ca 10 8b 10 26 49 0b 5a 08 90 1e 44
55 55 55 55 18 e4 75 d0 31 32 39 01 be 40 0e e2
55 55 55 55 42 37 5a 79 64 ea 05 f6 8e 00 f9 d9
55 55 55 55 2f 06 42 98 9c 0b 48 4d e7 42 86 38
55 55 55 55 ce 4b 7a 59 41 51 cf a3 93 3f d7 c3
55 55 55 55 ef 31 a9 7c 2b 63 55 78 b1 b8 53 e6
55 55 55 55 9b 27 a2 19 c7 1d 40 22 8e 34 01 d0
55 55 55 55 9b 24 14 7a 5c a5 35 8b 8c ba 0f ab
55 55 55 55 9c 32 a6 3c 49 78 93 2a 1a 4d 2b 31
55 55 55 55 74 16 c3 8a c4 62 49 37 59 3a a4 34
55 55 55 55 ad b6 94 5c 4a 01 60 10 52 6c e3 30
55 55 55 55 32 00 4b 7d b2 a1 36 50 81 61 a0 a1
55 55 55 55 ac 2d a6 fc 19 6d 50 c7 d3 0e ea 39
55 55 55 55 04 0e 08 ca 90 8b 78 57 d0 2e 28 7d
55 55 55 55 5a 9b e9 f5 27 e2 d1 b3 91 ae 82 a7
55 55 55 55 ca 0e 53 b0 8a fc 81 48 21 9c a4 19
55 55 55 55 08 a0 22 a7 d8 5e b8 71 ca 64 15 f1
55 55 55 55 1b 7b 54 47 2b a0 52 91 07 01 c4 68
55 55 55 55 e3 1a 4e aa 00 6b 23 a0 cc 9a 1a b0
55 55 55 55 e6 8c a1 4e 8e 05 a6 4b 72 10 76 67
55 55 55 55 39 2f 00 26 88 c4 aa 6c c6 53 c0 45
55 55 55 55 92 fe 36 a8 bd 4a b0 e9 cb 0c 78 75
55 55 55 55 c9 92 8c 45 1b 44 5b fb 49 b2 22 02
55 55 55 55 e0 00 6a 31 5a 28 51 0c 7a 40 8f 9f
55 55 55 55 81 cd 4e 19 02 68 0c 5f 61 81 8a c9
55 55 55 55 1b 68 f7 c8 49 32 c0 30 89 20 0b 62
55 55 55 55 b0 1a a5 2f 1c 3d ff 0a 06 2d 04 4a
55 55 55 55 86 c0 59 2c 88 84 5a c3 eb a9 ba 20
55 55 55 55 40 54 22 d8 53 5c 9b 48 dc 04 13 38

I must be addressing memory wrong, wouldn't you say?

pbreed:

I'm not using A0, if you're referring to the address line.

[SeeCwriter]

The problem appears to be with memcpy(). If I replace memcpy() with pointers, it all seems to work.

Code: Select all

 
BYTE *dst = (BYTE*)SRAM1_BASE_ADR;
BYTE *src = pattern;
WORD len = sizeof(pattern);

while( len-- > 0 ) *dst++ = *src++;