Optimize SDRAM Usage (MOD5272)

[DBrunermer]

Hi Everyone (MOD5272, Custom Carrier Board; NBEclipse NNDK 2.4 RC2)

The device I'm creating is a printhead controller, which means that essentially it's a data-pump with position tracking and a high-voltage pulse generator. I use the MOD5272 for network and memory, but have a custom CPLD for wave-form generation, quadrature encoder counting, and processor interrupt generation. I'm sending 1024 bits, 16 bits at a time to the CPLD, for 64 writes. On the downstream side, this is divided into (4) data paths, (8) bits wide each. So that means I'm really handling 128 byte bursts at the rate of about 2kHz. There's no color-depth, BTW, it's 1 pixel per bit B&W.

Ok, so here is what I want to optimize, and I'd like some thoughts about how and maybe some resources to learn more.

As it is, inside of the interrupt I have a very crude memory handler. It basically pulls the next word from the SDRAM, writes it to the destination port, and then goes back for the next one. I don't know much about SDRAM, but I know it's not the same as SRAM, and I'm wondering if I should be copying small snippets or blocks into something more local, and have these blocks somehow refreshed in between the interrupts.

I read the examples on DMA, and I'm not sure if that's what I should be doing, and if I did, where do I direct the data to go? My impression is that the very local cache is used by the OS, and I'll just out and out say that I'm not clear on how much memory there is in addition to the SDRAM, or if it's any faster. I'm sorry for not providing a whole pile of detail here (though I'm more than willing to) but I hate to leave the impression of having diarrhea of the fingertips. All of my older posts are actually about this project, and they describe the function better than I do here, but at the time I was building a simulation of the real thing on a DEV-KIT board. It's only now that I'm working with the final custom hardware that I have the time to start looking for better ways to do things.

Thanks much, Dan B.

[pbreed]

The SDRAM interface is the speed bottle neck on the 5272. (and 5270, 5234, and 5282)
Using DMA causes the system to swap bus masters cpu->dma engine -> cpu
Each of these transitions takes as long as 10 clock cycles on the SDRAM.

The system is actually faster if you don't use DMA and do the I/O as efficient writes from inside your code.
The code doing the writing is likely in the instruction cache and the data read from SDRAM is the only SDRAM access....

For the 5270,5234, and 5282 you can get some gains by playing games with code/databuffers in the onchip ram, 5272 this is not really and option.

Paul