I have taken the code advice form above and implement a simple class to access the external bus. I am trying to use d0-d15 as digital I/O whilst also accessing some 64k of byte wide SRAM using d24-d31. I am trying to test the code on the Mod-Dev-70 kit fitted with a MOD5270, I realise since there is no SRAM connected I won't be able to read anything back other than "undefined". The digital I/O should access the LED's and DIP switches ok.
However I am finding when my code reads the external bus I am getting an segmentation fault when it does the following instruction when reg a0=0xA0000000 :
moveb %a0@,%d0
ie trying to read a byte from 0xA0000000 is causing the fault.
Where has my understanding failed
I altered the value of CSCR_INIT and base address.This my code that does the prior initialisation, some of which is robbed from "ioboard.c" :
- #define DPRAM_ENABLE
#define IO_ENABLE
#define BASEADDRESS (0xA0000000)
#define CSCR_INIT 0x4941 // 8 bit transfers, AA, 2 IW, 1 SW, 1 SR
#define DPRAM1_BASEADDRESS (BASEADDRESS + 0x00000000)
#define DPRAM2_BASEADDRESS (DPRAM1_BASEADDRESS + 0x00010000)
#define IO_BASEADDRESS (BASEADDRESS + 0x00040000)
// Constructor
CExtBus::CExtBus()
{
bInitDone = FALSE ;
}
CExtBus::~CExtBus()
{
bInitDone = FALSE ;
}
void CExtBus::InitExtBus()
{
#ifdef DPRAM_ENABLE
// setup CS1 for DPRAM access
sim.cs[1].csar = (DPRAM1_BASEADDRESS >> 16);
sim.cs[1].cscr = CSCR_INIT;
sim.cs[1].csmr = 0x00000001;
#endif
#ifdef IO_ENABLE
// setup CS3 for I/O access
sim.cs[3].csar = (IO_BASEADDRESS >> 16 );
sim.cs[3].cscr = 0x2140; /* 0010 0001 0110 0000 */
sim.cs[3].csmr = 0x001F0001;
#endif
bInitDone = TRUE ;
}
volatile BYTE CExtBus::ReadExtBus(WORD address)
{
#ifdef DPRAM_ENABLE
return *( (unsigned char *)(DPRAM1_BASEADDRESS + address));
#else
return 0 ;
#endif
}