NetBurner Community Forum

Just wondering if this is still something that is being looked at?

pbreed wrote: ↑Mon Mar 01, 2021 5:07 pm Clearly there is a need for Gigabit we are evaluating several cpu families to satisfy this requirement....

How power sensitive are you?

How cost sensitive?

I'll go ahead and open a support case. Prior to and during configuration, the Altera Cyclone V are supposedly tri-stated, so hopefully it will not interfere with the MOD54417 boot. We've done some initial tests with an FPGA eval board where is seems to work (we're probably the ones who had trouble w...

Having ALE would be really helpful. The timing diagram (eg Fig 20-8 of RM) makes it look like the address is asserted for exactly 1 clock cycle during the address phase. But if that were not the case, I would have no way of generating ALE for exactly one pulse right before CS goes low on my own. I w...

Hello lgitlitz, Thanks for the detailed reply. Sounds like it might work. It does not change the board design, so I can always revert to 16-bit addr and 16-bit data if I need to. I had planned to do something similar to what you suggest on the FPGA side, but I don't think I need any wait states. I c...

We're connecting an FPGA to a MOD54417 module. We would greatly prefer to set the port size to 32-bits by setting the CSCR port size to "00". But I notice the platform reference says: The MOD5441x provides 16 address lines (A0-A15) and a 16-bit data bus (D16-D31) running in mode 2. An addr...

I guess my png attachment did not take.

Seems like it should work. I take it 0.65 Vcc = 2.145 confirms Vcc = 2.145 / 0.65 = 3.3 V for the flex bus voltage. But the MCF54417 data sheet seems to have different numbers. It has Vin high min = 0.51 * VDD instead of 0.65 * VDD. The 0.51 and 0.42 for the Vin high min and Vin low max and did seem...

We're connecting an FPGA to a MOD54417 via FlexBus. Unfortunately, newer FPGA's (20 nm and below) do no support 3.3 V LVCMOS. They max out at 3.0 V LVCMOS and the Altera Cyclone 10, Arria 10 etc chips only have 48 of those. Looking at the MOD54417 data sheet, it should still work so long as the Flex...

SOM's with PCIe often use an edge connector with PCIe lanes as well as other things (ie GPIO, SPI etc). That would work well but tends to limit how many signals are available. There are of course other possibilities. We would prefer not have any cabling from the SOM to our baseboard. Note that we wo...

I would GREATLY prefer the option of your tools ported to an FPGA SoC! I used Xilinx tools for many years and we considered Zynq. The Xilinx embedded tools are actually pretty good. Nothing approaching yours, but getting FreeRTOS working is fairly easy. The problem is on the FPGA side where Vivado i...